ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 72

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

eZ80F91 ASSP
Product Specification
64
GPIO Port Interrupts
All interrupts are latched. In effect, an interrupt is held even if the interrupt occurs while
another interrupt is being serviced and interrupts are disabled, or if the interrupt is of a
lower priority. However, before the latched ISR completes its task or re-enables interrupts,
the ISR must clear the interrupt. For on-chip peripherals, the interrupt is cleared when the
data register is accessed. For GPIO-level interrupts, the interrupt signal must be removed
before the ISR completes its task. For GPIO-edge interrupts (single and dual), the interrupt
is cleared by writing a 1 to the corresponding bit position in the Px_ALT0 register. See
Edge Triggered Interrupts
on page 54.
For F91 devices with a ZDI or JTAG revision less than 2, care must be taken using a GPIO
Note:
data register when it is configured for interrupts. For edge-interrupt modes (modes 6 and 9)
as discussed earlier, writing 1 clears the interrupt. However, 1 in the data register also con-
veys a particular configuration. For example, when the data register Px_DR is set first fol-
lowed by the Px_ALT2, Px_ALT1, and Px_DDR registers, then the configuration is
performed correctly. Writing 1 to the register later to clear interrupts does not change the
configuration. For F91 devices with a ZDI or JTAG revision 2 or later, the clearing of inter-
rupts is accomplished through the new Px_ALT0 registers and the above problem does not
exist.
In mode 9 operation, if the GPIO is already configured for mode 9 and if the trigger edge
must be changed (from falling to rising or from rising to falling), then the configuration
must be changed to another mode, such as Mode 2, and then changed back to mode 9. For
example, enter mode 2 by writing the registers in the sequence PxDR, Px_ALT2,
Px_ALT1, Px_DDR. Next, change back to mode 9 by writing the registers in the sequence
PxDR, Px_ALT2, Px_ALT1, Px_DDR.
In Mode 8 operation, if the GPIO is configured for level-sensitive interrupts, a Write value
to Px_DR after configuration must be the same Write value used when configuring the
GPIO.
PS027001-0707
Interrupt Controller