ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 342

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 223. EMAC Transmit Read Pointer Register—High Byte
PS027001-0707
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
EMAC_TRP_H
EMAC Transmit Read Pointer Register—High Byte
Because of the size of the EMAC’s 8 KB SRAM, the upper three bits of the EMAC Trans-
mit Read Pointer Register are always zero. See
EMAC Receive Blocks Left Register—Low and High Bytes
This register reports the number of buffers left in the Receive EMAC shared memory. The
hardware uses this information along with the block-level set in the EMAC_BUFSZ regis-
ter to determine when to transmit a pause control frame. Software uses this information to
determine when it must request that a pause control frame be transmitted (by setting bit 6
of the EMAC_CFG4 register). For the BlksLeft logic to operate properly, the Receive
buffer must contain at least one more packet buffer than the number of packet buffers
required for the largest packet. That is, one packet cannot fill the entire Receive buffer.
Otherwise, the BlksLeft will be in error. See
Value
00h–1Fh These bits represent the High byte of the 2 byte EMAC
RO
7
0
Description
TxDMA
EMAC_TRP_L}. Bit 7 is bit 15 (msb) of the 16 bit value. Bit
0 is bit 8 of the 16 bit value.
RO
6
0
Transmit Read Pointer
RO
5
0
RO
4
0
RO
3
0
Table 224
value, {EMAC_TRP_H,
Table
RO
2
0
223.
and
(EMAC_TRP_H = 0054h)
Table 225
Ethernet Media Access Controller
RO
1
0
Product Specification
RO
0
0
on page 335.
eZ80F91 ASSP
334