ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 92
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ez80f91
Manufacturer Part Number
ez80f91
Description
Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
Manufacturer
ZiLOG Semiconductor
Datasheet
1.EZ80F91.pdf
(387 pages)
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PS027001-0707
System Clock
ADDR[23:0]
DATA[7:0]
or IORQ
DTACK
MREQ
CSx
R/W
DS
AS
Switching Between Bus Modes
When switching bus modes between Intel™ to Motorola, Motorola to Intel™, eZ80 to
Motorola, or eZ80 to Intel™, there is one extra SCLK cycle added to the bus access. An
extra clock cycle is not required for repeated access in any of the bus modes (for example,
Intel™ to Intel™). An extra clock cycle is not required for Intel™ (or Motorola) to eZ80
bus mode (under normal operation). The extra clock cycle is not shown in the timing
examples. Due to the asynchronous nature of these bus protocols, the extra delay does not
impact peripheral communication.
Figure 19. Example: Motorola Bus Mode Write Timing
S0
S1
S2
S3
S4
S5
Chip Selects and Wait States
Product Specification
S6
eZ80F91 ASSP
S7
84
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