ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 261

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 140. ZDI Bus Control Register (ZDI_BUS_CTL = 17h in the ZDI Register Write Only
Address Space)
PS027001-0707
Bit
Reset
CPU Access
Note: W = Write Only.
Bit
Position
7
ZDI_BUSAK_EN
6
ZDI_BUSAK
[5:0]
ZDI Bus Control Register
The ZDI Bus Control register controls bus requests during DEBUG mode. It enables or
disables bus acknowledge in ZDI DEBUG mode and allows ZDI to force assertion of the
BUSACK signal. This register must only be written during ZDI Debug mode (that is, fol-
lowing a break). See
Instruction Store 4:0 Registers
The ZDI Instruction Store registers are located in the ZDI Register Write Only address
space. They are written with instruction data for direct execution by the CPU. When the
ZDI_IS0 register is written, the eZ80F91 device exits the ZDI break state and executes a
single instruction. The opcodes and operands for the instruction come from these Instruc-
tion Store registers. The Instruction Store Register 0 is the first byte fetched, followed by
Instruction Store registers 1, 2, 3, and 4, as necessary. Only the bytes the CPU requires to
execute the instruction must be stored in these registers. Some CPU instructions, when
combined with the MEMORY mode suffixes (.SIS, .SIL, .LIS, or .LIL), require 6 bytes to
operate. These 6-byte instructions cannot be executed directly using the ZDI Instruction
Store registers. See
Value
0
1
0
1
000000
W
7
0
Description
Bus requests by external peripherals using the BUSREQ
pin are ignored. The bus acknowledge signal, BUSACK, is
not asserted in response to any bus requests.
Bus requests by external peripherals using the BUSREQ
pin are accepted. A bus acknowledge occurs at the end of
the current ZDI operation. The bus acknowledge is
indicated by asserting the BUSACK pin in response to a
bus request.
Deassert the bus acknowledge pin (BUSACK) to return
control of the address and data buses back to ZDI.
Assert the bus acknowledge pin (BUSACK) to pass control
of the address and data buses to an external peripheral.
Reserved.
W
6
0
Table
Table
141.
140.
W
5
0
W
4
0
W
3
0
W
2
0
W
1
0
Product Specification
W
0
0
Zilog Debug Interface
eZ80F91 ASSP
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