ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 305

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
•
Figure 60
The Transmit and Receive buffers are subdivided into packet buffers of 32, 64, 128, or 256
bytes in size. The packet buffer size is set in bits 7 and 6 of the EmacBufSize register. An
Ethernet packet accommodate multiple packet buffers. First, however, a brief listing of the
contents of a typical Ethernet packet is in order. See
Table 177. Ethernet Packet Contents
At the start of each packet is a descriptor table that describes the packet. Each actual
Ethernet packet follows the descriptor table as illustrated in
Byte Range
Bytes 0–5
Bytes 6–11
Bytes 12–13
Bytes 14–n
Bytes (n+1)–(n+4)
RHBP
TLBP
Receive High Boundary Pointer (RHBP)—this register points to the end of the Receive
buffer + 1.
BP
displays the internal Ethernet shared memory.
Figure 60. Internal Ethernet Shared Memory
Contents
MAC destination address.
MAC source address.
Length/Type field.
MAC Client Data.
Frame Check Sequence.
Rx Buffer
Tx Buffer
Upper Memory Address
Lower Memory Address
Table
177.
Ethernet Media Access Controller
Figure 61
Product Specification
on page 298.
eZ80F91 ASSP
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