ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 335

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 214. EMAC Buffer Size Register
PS027001-0707
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:6]
BUFSZ
[5:0]
TPCF_LEV
EMAC Interrupt Enable Register
Enabling the Receive Overrun interrupt allows software to detect an overrun condition
as soon as it occurs. If this interrupt is not set, then an overrun cannot be detected until
the software processes the Receive packet with the overrun and checks the Receive sta-
tus in the Rx descriptor table. Because the receiver is disabled by an overrun error until
the Rx_OVR bit is cleared in the EMAC_ISTAT register, this packet is the final packet
in the Receive buffer. To re-enable the receiver before all of the Receive packets are
processed and the Receive buffer is empty, software enables this interrupt to detect the
overrun condition early. As it processes the Receive packets, it re-enables the receiver
when the number of free buffers is greater than the number of minimum buffers. See
Table 215
Value
00
01
10
11
00h–3Fh Transmit Pause Control Frame level. 00h disables the
R/W
Description
Set EMAC Rx/Tx buffer size to 256 bytes.
Set EMAC Rx/Tx buffer size to 128 bytes.
Set EMAC Rx/Tx buffer size to 64 bytes.
Set EMAC Rx/Tx buffer size to 32 bytes.
hardware generated transmit pause control frame.
on page 328.
7
0
R/W
6
0
R/W
5
0
(EMAC_BUFSZ = 004Bh)
R/W
4
0
R/W
3
0
R/W
2
0
R/W
Ethernet Media Access Controller
1
0
Product Specification
R/W
0
0
eZ80F91 ASSP
327