ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 55

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 4. Clock Peripheral Power-Down Register 1
PS027001-0707
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit Position
7
GPIO_D_OFF
6
GPIO_C_OFF
5
GPIO_B_OFF
4
GPIO_A_OFF
3
SPI_OFF
2
I2C_OFF
1
UART1_OFF
0
UART0_OFF
Value Description
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
R/W
System clock to GPIO Port D is powered down.
Port D alternate functions do not operate correctly.
System clock to GPIO Port D is powered up.
System clock to GPIO Port C is powered down.
Port C alternate functions do not operate correctly.
System clock to GPIO Port C is powered up.
System clock to GPIO Port B is powered down.
Port B alternate functions do not operate correctly.
System clock to GPIO Port B is powered up.
System clock to GPIO Port A is powered down.
Port A alternate functions do not operate correctly.
System clock to GPIO Port A is powered up.
System clock to SPI is powered down.
System clock to SPI is powered up.
System clock to I
System clock to I
System clock to UART1 is powered down.
System clock to UART1 is powered up.
System clock to UART0 and IrDA endec is powered down.
System clock to UART0 and IrDA endec is powered up.
7
0
R/W
6
0
R/W
2
2
5
0
C is powered down.
C is powered up.
R/W
4
0
(CLK_PPD1 = 00DBh)
R/W
3
0
R/W
2
0
R/W
1
0
Product Specification
R/W
0
0
eZ80F91 ASSP
Low-Power Modes
47