ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 215

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
SPI Baud Rate Generator
Data Transfer Procedure with SPI Configured as a Master
4. If the SPI interrupt is enabled by setting IRQ_EN (SPI_CTL[7]) High, an SPI inter-
Clearing the Mode Fault flag is performed by reading the SPI Status register. The other
SPI control bits (SPI_EN and MASTER_EN) must be restored to their original states by
user software after the Mode Fault Flag is cleared to 0.
Write Collision
The write collision flag, WCOL (SPI_SR[5]), is set to 1 when an attempt is made to write
to the SPI Transmit Shift register (SPI_TSR) while data transfer occurs. Clearing the
WCOL bit is performed by reading SPI_SR with the WCOL bit set to 1.
The SPI’s Baud Rate Generator (BRG) creates a lower frequency clock from the high-fre-
quency system clock. The BRG output is used as the clock source by the SPI.
Baud Rate Generator Functional Description
The SPI’s BRG consists of a 16-bit downcounter, two 8-bit registers, and associated
decoding logic. The BRG’s initial value is defined by the two BRG Divisor Latch registers
{SPI_BRG_H, SPI_BRG_L}. At the rising edge of each system clock, the BRG decre-
ments until it reaches the value
reloads the initial value from {SPI_BRG_H, SPI_BRG_L) and outputs a pulse to indicate
the end of the count.
The SPI Data Rate is calculated using the following equation:
Upon RESET, the 16-bit BRG divisor value resets to
a Master, the BRG divisor value must be set to a value of
is operating as a Slave, the BRG divisor value must be set to a value of
A software Write to either the Low- or High-byte registers for the BRG Divisor Latch
causes both the Low and High bytes to load into the BRG counter, and causes the count to
restart.
The following list describes the procedure for transferring data from a master SPI device
to a slave SPI device.
rupt is generated.
SPI Data Rate (bits/s)
=
0001h
2 X SPI Baud Rate Generator Divisor
System Clock Frequency
. On the next system clock rising edge, the BRG
0002h
0003h
. When the SPI is operating as
Product Specification
or greater. When the SPI
Serial Peripheral Interface
0004h
eZ80F91 ASSP
or greater.
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