ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 267

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 148. ZDI Bus Control Register
Address Space)
PS027001-0707
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
7
ZDI_BUSAcK_En
6
ZDI_BUS_STAT
[5:0]
ZDI Bus Status Register
The ZDI Bus Status register monitors BUSACKs during DEBUG mode. See
ZDI Read Memory Register
When a Read is executed from the ZDI Read Memory register, the eZ80F91 device
fetches the data from the memory address currently pointed to by the Program
Counter, PC; the Program Counter is then incremented. In Z80 MEMORY mode, the
memory address is {MBASE, PC[15:0]}. In ADL MEMORY mode, the memory
address is PC[23:0]. For more information on Z80 and ADL MEMORY modes, refer
to the eZ80
gram Counter, PC, increments after each data Read. However, the ZDI register address
does not increment automatically when this register is accessed. As a result, the ZDI
master reads any number of data bytes out of memory via the ZDI Read Memory reg-
ister. See
Value
0
1
0
1
000000
Table 149
®
R
7
0
CPU User Manual (UM0077) available on www.zilog.com. The Pro-
Description
Bus requests by external peripherals using the
BUSREQ pin are ignored. The bus acknowledge signal,
BUSACK, is not asserted.
Bus requests by external peripherals using the
BUSREQ pin are accepted. A bus acknowledge occurs
at the end of the current ZDI operation. The bus
acknowledge is indicated by asserting the BUSACK pin.
Address and data buses are not relinquished to an
external peripheral. bus acknowledge is deasserted
(BUSACK pin is High).
Address and data buses are relinquished to an external
peripheral. bus acknowledge is asserted (BUSACK pin
is Low).
Reserved.
R
6
0
on page 260.
(ZDI_BUS_STAT = 17h in the ZDI Register Read Only
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
Product Specification
R
0
0
Zilog Debug Interface
eZ80F91 ASSP
Table
148.
259