ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 241

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 131. I
PS027001-0707
Bit
Reset
CPU Access
Note: W = Write Only.
Bit
Position
[7:0]
SRR
2
C Software Reset Register
programmable clock divider stages, a high sampling frequency is ensured while allowing
the MASTER mode output to be set to a lower frequency.
Bus Clock Speed
The I
To ensure correct detection of START and STOP conditions on the bus, the I
ple the I
bus. The sampling frequency must therefore be at least 1 MHz (4 MHz in FAST mode) to
guarantee correct operation with other bus masters.
The I
and the value in the I
MASTER mode is determined by the frequency of the input clock and the values in
I
I
The I
a software reset of the I
2
2
C Software Reset Register
C_CCR[2:0] and I
Value
00h–FFh Writing any value to this register performs a software reset
2
2
2
C bus is defined for bus clock speeds up to 100 kbps (400 kbps in FAST mode).
C sampling frequency is determined by the frequency of the eZ80F91 system clock
C_SRR register is a Write Only register. Writing any value to this register performs
2
X
W
C bus at least ten times faster than the bus clock speed of the fastest master on the
7
Description
of the I
X
W
6
2
2
2
C_CCR[6:3].
C_CCR bits 2 to 0. The bus clock speed generated by the I
C module.
2
C module. See
X
W
5
(I2C_SRR = 00CDh)
X
W
4
Table
X
W
3
131.
X
W
2
X
W
1
Product Specification
X
W
0
I
2
C Serial I/O Interface
eZ80F91 ASSP
2
C must sam-
2
C in
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