ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 262

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 141. Instruction Store 4:0 Registers
ZDI_IS1 = 24h, and ZDI_IS0 = 25h in the ZDI Register Write Only Address Space)
PS027001-0707
Bit
Reset
CPU Access
Note: X = Undefined; W = Write.
Bit
Position
[7:0]
zdi_is4,
zdi_is3,
zdi_is2,
zdi_is1,
or
zdi_is0
Note:
The Instruction Store 0 register is located at a higher ZDI address than the other Instruc-
tion Store registers. This feature allows the use of the ZDI auto-address increment function
to load and execute a multibyte instruction with a single data stream from the ZDI master.
Execution of the instruction commences with writing the final byte to ZDI_IS0.
ZDI Write Memory Register
A Write to the ZDI Write Memory register causes the eZ80F91 device to write the 8-bit
data to the memory location specified by the current address in the Program Counter. In
Z80 MEMORY mode, this address is {MBASE, PC[15:0]}. In ADL MEMORY mode,
this address is PC[23:0]. The Program Counter, PC, increments after each data Write.
However, the ZDI register address does not increment automatically when this register
is accessed. As a result, the ZDI master is allowed to write any number of data bytes by
writing to this address one time followed by any number of data bytes. See
on page 255.
Value
00h–FFh These registers contain the Op Codes and operands for
W
X
7
Description
immediate execution by the CPU following a Write to
ZDI_IS0. The ZDI_IS0 register contains the first Op Code
of the instruction. The remaining ZDI_ISx registers
contain any additional Op Codes or operand dates
required for execution of the required instruction.
W
X
6
W
X
5
(ZDI_IS4 = 21h, ZDI_IS3 = 22h, ZDI_IS2 = 23h,
W
X
4
W
X
3
W
X
2
W
X
1
Product Specification
W
X
0
Zilog Debug Interface
eZ80F91 ASSP
Table 142
254