ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 61

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

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PS027001-0707
Mode 7(Input)
Mode 2
Mode 6
Mode 8
Mode 9
System Clock
* Writing to the Px_DR stores
Data
* Reading from the Px_DR returns
Alternate Function Output
the value stored in this register
the value in this register
D
Px_DR*
Figure 6. GPIO Port Pin Block Diagram for Output and Input/Output Mode
Figure 5. GPIO Port Pin Block Diagram for Input and Interrupt Modes
Q
Q
Simplified GPIO Port Block Diagram for Modes 1, 3, 4 and 7 (Output)
Mode 3
Mode 4
Mode 1
Mode 7 (Output)
GPIO Output Buffer
Tristated for
modes 2,6,8,9
and 7(Input)
ENB
SysClock
Default Value
Mode 7(Input)
Clear Interrupt
Modes 6,8,9
D
GPIO Port Pin
Q
GPIO Output Buffer
Px_DR*
D
ENB
Q
General Purpose Input/Output
Product Specification
GPIO Port
Pin
Interrupt
Logic
External Pull-up
(Open source)
eZ80F91 ASSP
Required for
Input to chip
VDD
Mode 4
Alternate
Function
Input
Interrupt
Required for
(open drain)
External
Pull-up
Mode 3
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