ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 33

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
Table 2. Pin Identification on the eZ80F91 Device (Continued)
LQFP
Pin No
143
144
System Clock Source Options
BGA
Pin No Symbol
B3
A2
The following section describes the system clock source options.
System Clock—
all internal logic. The SCLK source can be an external crystal oscillator, an internal PLL,
or an internal 32 kHz RTC oscillator. The SCLK source is selected by PLL Control Regis-
ter 0. RESET default is provided by the external crystal oscillator. For more details on
CLK_MUX values in the PLL Control Register 0, see
PHI—
the eZ80F91 device. PHI is used as the reference clock for all AC characteristics, see
page 348.
External Crystal Oscillator—
one mode, the X
is not connected. In the other mode, the X
Crystals recommended by Zilog are defined to be a 50 MHz–3 overtone circuit or 1–10
339.
Real Time Clock—
the on-chip 32768 Hz crystal oscillator or a 50/60 Hz power-line frequency input. While
intended for timekeeping, the RTC 32 kHz oscillator is selected as an SCLK. RTC_V
and RTC_V
loss of line power when a battery is provided. For more details, see
page 339.
MHz range fundamental for PLL operation. For details, see
MDIO
WP
PHI is a device output driven by SCLK that is used for system synchronization to
SS
provides an isolated power supply to ensure RTC operation in the event of
IN
Function
Write Protect
MII
Management
Data
The eZ80F91 device’s internal clock, SCLK, is responsible for clocking
pin is driven by a oscillator from DC up to 50 MHz when the X
An internal 32 kHz real-time clock crystal oscillator driven by either
An externally-driven oscillator operates in two modes. In
Signal Direction Description
Bidirectional
Schmitt-trigger
input, Active Low
IN
and X
OUT
This pin is used by the Ethernet
MAC for the MII Management
Interface to the PHY. The Ethernet
MAC sends and receives the MII
Management Data to and from the
MII PHY interface.
The Write Protect input is used by
the Flash Controller to protect the
Boot Block from Write and ERASE
operations.
Table 154
pins are driven by a crystal circuit.
On-Chip Oscillators
Product Specification
on page 273.
On-Chip Oscillators
Architectural Overview
eZ80F91 ASSP
on page
OUT
DD
pin
on
25