ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 82

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 21. Intel Bus Mode Read States—Separate Address and Data Buses
PS027001-0707
STATE T1
STATE T2
The Read cycle begins in State T1. The CPU drives the address onto the address bus and
the associated chip select signal is asserted. The CPU drives the ALE signal High at the
beginning of T1. In the middle of T1, the CPU drives ALE Low to facilitate the latching of the
address.
During State T2, the CPU asserts the RD signal. Depending on the instruction, either the
MREQ or IORQ signal is asserted.
Intel Bus Mode—Separate Address and Data Buses
During Read operations with separate address and data buses, the Intel bus mode employs
4 states—T1, T2, T3, and T4 as described in
eZ80 Bus Mode
Signals (Pins)
ADDR[23:0]
DATA[7:0]
INSTRD
MREQ
IORQ
WAIT
WR
RD
Figure 12. Intel Bus Mode Signal and Pin Mapping
Multiplexed
Bus Mode
Controller
Controller
Bus
ADDR[7:0]
Table
21.
Intel Bus
Signal Equvalents
ALE
RD
WR
READY
MREQ
IORQ
ADDR[23:0]
DATA[7:0]
Chip Selects and Wait States
Product Specification
eZ80F91 ASSP
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