ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 283

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 155. PLL Control Register 1
.
PS027001-0707
Bit
Reset
CPU Access
Note: R = Read Only; R/W = Read/Write.
Bit
Position
[7:6]
5
LCK_STATUS
4
INT_LOCK
3
INT_UNLOCK
2
INT_LOCK_EN
1
INT_UNLOCK_
EN
0
PLL_ENABLE
Note
1. PLL cannot be disabled if the CLK_MUX bit of PLL_CTL0[1:0] is set to 01, because the PLL is
selected as the clock source.
Value Description
00
0
1
0
1
0
1
0
1
0
1
0
1
Reserved.
PLL is currently out of lock.
PLL is currently locked.
Lock signal from PLL has not risen since last time register was
read.
Interrupt generated when PLL enters LOCK mode. Held until
register is read.
Lock signal from PLL has not fallen since last time register was
read
Interrupt generated when PLL goes out of lock. Held until
register is read.
Interrupt generation for PLL locked condition (Bit 4) is disabled.
Interrupt generation for PLL locked condition is enabled.
Interrupt generation for PLL unlocked condition (Bit 3) is
disabled.
Interrupt generation for PLL unlocked condition is enabled.
PLL is disabled.
PLL is enabled.
R
7
0
R
6
0
(PLL_CTL1 = 005Fh)
1
R
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
Product Specification
R/W
0
0
Phase-Locked Loop
eZ80F91 ASSP
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