ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 143

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
Timer Interrupt Identification Register
The TImer x Interrupt Identification Register (see
that the CPU determines the cause of a timer interrupt. This register is cleared by a CPU
Read.
Table 56. Timer Interrupt Identification Register
0067h, TMR2_IIR = 0071h, TMR3_IIR = 0076h)
Bit
Reset
CPU Access
Note: R = Read only;
Bit
Position
7
6
OC3
5
OC2
4
OC1
3
OC0
2
ICB
1
ICA
0
EOC
Value
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
Unused.
Output compare, OC3, does not occur.
Output compare, OC3, occurs.
Output compare, OC2, does not occur.
Output compare, OC2, occurs.
Output compare, OC1, does not occur.
Output compare, OC1, occurs.
Output compare, OC0, does not occur.
Output compare, OC0, occurs.
Input capture, ICB, does not occur.
For Timer 1, the capture pin is IC1.
For Timer 3, the capture pin is IC3.
Input capture, ICB, occurs.
For Timer 1, the capture pin is IC1.
For Timer 3, the capture pin is IC3.
Input capture, ICA, or PWM power trip does not occur.
For Timer 1, the capture pin is IC0.
For Timer 3, the capture pin is IC2.
Input capture, ICA, or PWM power trip occurs.
For Timer 1, the capture pin is IC0.
For Timer 3, the capture pin is IC2.
End-of-count does not occur.
End-of-count occurs.
R
7
0
R
6
0
R
5
0
Table
R
4
0
56) is used to flag timer events so
(TMR0_IIR = 0062h, TMR1_IIR =
R
3
0
Programmable Reload Timers
Product Specification
R
2
0
eZ80F91 ASSP
R
1
0
R
0
0
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