ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 29

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ez80f91

Manufacturer Part Number
ez80f91
Description
Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
Manufacturer
ZiLOG Semiconductor
Datasheet

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PS027001-0707
Table 2. Pin Identification on the eZ80F91 Device (Continued)
LQFP
Pin No
117
118
119
B9
A9
C9
BGA
Pin No Symbol
PA3
PWM3
OC3
PA4
PWM0
TOUT0
PA5
PWM1
TOUT2
Function
GPIO Port A
GPIO Port A
GPIO Port A
PWM Output 3 Output
Output
Compare 3
PWM Output 0
Inverted
Timer Out
PWM Output 1
Inverted
Timer Out
Signal Direction Description
Bidirectional
Output
Bidirectional
Output
Output
Bidirectional
Output
Output
This pin is used for GPIO. It is
individually programmed as input or
output and is also used individually
as an interrupt input. Each Port A
pin, when programmed as output is
selected to be an open-drain or
open-source output.
This pin is used by Timer 3 for PWM
3. This signal is multiplexed with
PA3.
This pin is used by Timer 3 for
Output Compare 3 This signal is
multiplexed with PA3.
This pin is used for GPIO. It is
individually programmed as input or
output and is also used individually
as an interrupt input. Each Port A
pin, when programmed as output is
selected to be an open-drain or
open-source output.
This pin is used by Timer 3 for
negative PWM 0. This signal is
multiplexed with PA4.
This pin is used by Timer 0 timer-out
signal. This signal is multiplexed
with PA4.
This pin is used for GPIO. It is
individually programmed as input or
output and is also used individually
as an interrupt input. Each Port A
pin, when programmed as output is
selected to be an open-drain or
open-source output.
This pin is used by Timer 3 for
negative PWM 1. This signal is
multiplexed with PA5.
This pin is used by the Timer 2
timer-out signal. This signal is
multiplexed with PA5.
Product Specification
Architectural Overview
eZ80F91 ASSP
21

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