ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 83

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 21. Intel Bus Mode Read States—Separate Address and Data Buses (Continued)
Table 22. Intel Bus Mode Write States—Separate Address and Data Buses
PS027001-0707
STATE T3
STATE T4
STATE T1
STATE T2
STATE T3
STATE T4
During State T3, no bus signals are altered. If the external READY (WAIT) pin is driven Low
During State T3, no bus signals are altered. If the external READY (WAIT) pin is driven Low
The CPU deasserts the WR signal at the beginning of State T4. The CPU holds the data
at least one CPU system clock cycle prior to the beginning of State T3, additional wait states
(T
The CPU latches the Read data at the beginning of State T4. The CPU deasserts the RD
signal and completes the Intel bus mode cycle.
The Write cycle begins in State T1. The CPU drives the address onto the address bus, the
associated chip select signal is asserted, and the data is driven onto the data bus. The CPU
drives the ALE signal High at the beginning of T1. During the middle of T1, the CPU drives
ALE Low to facilitate the latching of the address.
During State T2, the CPU asserts the WR signal. Depending on the instruction, either the
MREQ or IORQ signal is asserted.
at least one CPU system clock cycle prior to the beginning of State T3, additional wait states
(T
and address buses till the end of T4. The bus cycle is completed at the end of T4.
WAIT
WAIT
During Write operations with separate address and data buses, the Intel bus mode employs
4 states—T1, T2, T3, and T4 as described in
Intel bus mode timing is illustrated for a Read operation in
Write operation in
driven Low prior to the beginning of State T3, additional wait states (T
until the READY signal is driven High. The Intel bus mode states are configured for 2 to
15 CPU system clock cycles. In the
Intel bus mode state is 2 CPU system clock cycles in duration.
Figure 14
peripheral.
) are asserted until the READY pin is driven High.
) are asserted until the READY pin is driven High.
on page 77 also illustrate the assertion of one Wait state (T
Figure 14
on page 76. If the READY signal (external WAIT pin) is
Figure 13
Table
on page 76 and
22.
Figure 13
Figure 14
Figure 13
Chip Selects and Wait States
Product Specification
WAIT
on page 76 and for a
WAIT
on page 77, each
eZ80F91 ASSP
on page 76 and
) by the selected
) are asserted
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