ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 193

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 98. UART Interrupt Enable Registers
PS027001-0707
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:5]
4
TCIE
3
MIIE
2
LSIE
1
TIE
0
RIE
Value
000
0
1
0
1
0
1
0
1
0
1
Description
Reserved
Transmission complete interrupt is disabled
Transmission complete interrupt is generated when both the transmit hold
register and the transmit shift register are empty
Modem interrupt on edge detect of status inputs is disabled.
Modem interrupt on edge detect of status inputs is enabled.
Line status interrupt is disabled.
Line status interrupt is enabled for receive data errors: incorrect parity bit
received, framing error, overrun error, or break detection.
Transmit interrupt is disabled.
Transmit interrupt is enabled. Interrupt is generated when the transmit
FIFO/buffer is empty indicating no more bytes available for transmission.
Receive interrupt is disabled.
Receive interrupt and receiver time-out interrupt are enabled. Interrupt is
generated if the FIFO/buffer contains data ready to be read or if the
receiver times out.
R/W
7
0
R/W
6
0
R/W
(UART0_IER = 00C1h, UART1_IER = 00D1h)
5
0
R/W
4
0
Universal Asynchronous Receiver/Transmitter
R/W
3
0
R/W
Product Specification
2
0
eZ80F91 ASSP
R/W
1
0
R/W
0
0
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