ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 325

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 198. EMAC MII Management Register (EMAC_MIIMGT = 003Bh)
PS027001-0707
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
7
LCTLD
6
RSTAT
5
SCINC
4
SCAN
3
SPRE
EMAC MII Management Register
The EMAC MII Management Register is used to control the external PHY attached to the
MII. See
Value
1
0
1
0
1
0
1
0
1
0
Table
R/W
Description
Rising edge causes the CTLD control data to be transmitted to
external PHY if MII is not busy. This bit is self clearing.
No operation.
Rising edge causes status to be read from external PHY via
PRSD[15:0] bus if MII is not busy. This bit is self clearing.
No operation.
Scan PHY address increments upon SCAN cycle. The SCAN
bit must also be set for the PHY address to increment after
each scan. The scanning starts at the EMAC_FIAD and
increments up to 1Fh. It then returns to the EMAC_FIAD
address.
Normal operation.
Perform continuous Read cycles via MII management. While in
SCAN mode, the EMAC_ISTAT[MGTDONE] bit is set when the
current PHY Read has completed. At this time, the
EMAC_PRSD register holds the Read data and the
EMAC_MIISTAT[4:0] holds the address of the PHY for which
the EMAC_PRSD data pertains.
Normal operation.
Suppress the MDO preamble. MDO is management data
output, an internal signal driven from the MDIO pin.
Normal preamble.
7
0
198.
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
Ethernet Media Access Controller
1
0
Product Specification
R/W
0
0
eZ80F91 ASSP
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