ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 68

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 13. Vectored Interrupt Operation (Continued)
PS027001-0707
Memory
Mode
ADL Mode
ADL
Bit
1
Interrupt Priority Registers
The eZ80F91 provides two interrupt priority levels for the maskable interrupts. The default
priority (or Level 0) is indicated in
maskable interrupt increases to Level 1 (a higher priority than any Level 0 interrupt) by
setting the appropriate bit in the Interrupt Priority registers as shown in
MADL
Bit
1
Read the LSB of the interrupt vector placed on the internal vectored interrupt
bus, IVECT [8:0], by the interrupting peripheral.
•
•
• The Starting Program Counter is PC[23:0].
• Push the 3-byte return address, PC[23:0], onto the SPL stack.
• Push a 01h byte onto the SPL stack to indicate a restart from ADL mode
• The ADL mode bit remains set to 1.
• The interrupt vector address is located at {I[15:1], IVECT[8:0]}.
• PC[23:0]
• The interrupt service routine must end with RETI.L
Operation
IEF1
IEF2
(because ADL = 1).
←
←
0
0
←
( { I[15:1], IVECT[8:0] } )
Table 14
on page 61. The default priority of any
.
Product Specification
Table 14
eZ80F91 ASSP
Interrupt Controller
on page 61.
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