ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 185

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

eZ80F91 ASSP
Product Specification
177
parameters for the protocol from the bits programmed via the UARTx_LCTL register.
When enabled, an interrupt is generated after the final protocol bit is transmitted which the
CPU resets by loading data into the UARTx_THR register. The TxD output is set to 1 if
the transmitter is idle (that is, the transmitter does not contain any data to be transmitted).
The transmitter operates with the BRG clock. The data bits are placed on the TxD output
one time every 16 BRG clock cycles. The transmitter block also implements a parity gen-
erator that attaches the parity bit to the byte, if programmed. For 9-bit data, the host CPU
programs the parity bit generator so that it marks the byte as either address (mark parity)
or data (space parity).
UART Receiver
The receiver block controls the data reception from the RxD signal. The receiver block
implements a receiver shift register, receiver line error condition monitoring logic and
receiver data ready logic. It also implements the parity checker.
The UARTx_RBR is a Read Only register of the module. The CPU reads received data
from this register. The condition of the UARTx_RBR register is monitored by the DR bit
(bit 0 of the UARTx_LSR register). The DR bit is 1 when a data byte is received and trans-
ferred to the UARTx_RBR register from the receiver shift register. The DR bit is reset
only when the CPU reads all of the received data bytes. If the number of bits received is
less than eight, the unused most-significant bits of the data byte Read are 0.
For 9-bit data, the receiver checks incoming bytes for space parity. A line status interrupt
is generated when an address byte is received, because address bytes maintain high parity
bits. The CPU clears the interrupt by determining if the address matches its own, then con-
figures the receiver to either accept the subsequent data bytes if the address matches, or
ignore the data if the address does not match.
The receiver uses the clock from the BRG for receiving the data. This clock must operate
at 16 times the appropriate baud rate. The receiver synchronizes the shift clock on the fall-
ing edge of the RxD input start bit. It then receives a complete byte according to the set
parameters. The receiver also implements logic to detect framing errors, parity errors,
overrun errors, and break signals.
UART Modem Control
The modem control logic provides two outputs and four inputs for handshaking with the
modem. Any change in the modem status inputs, except RI, is detected and an interrupt is
generated. For RI, an interrupt is generated only when the trailing edge of the RI is
detected. The module also provides LOOP mode for self-diagnostics.
PS027001-0707
Universal Asynchronous Receiver/Transmitter