HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 105

• Manufacturer Part Number: HD6475328-CP10
• Description: original Hitachi CMOS microcomputer unit (MCU)
• Manufacturer: HITACHI [Hitachi Semiconductor]

Maximum Mode: Two words are read from addresses H'0000 to H'0003 in the vector table. The
byte in address H'0000 is ignored. The byte in address H'0001 is copied to the code page register
(CP). The contents of addresses H'0002 and H'0003 are copied to the program counter. Program
execution starts from the address indicated by the code page register and program counter.
Figure 4-3 shows the timing of the reset sequence in minimum mode. Figure 4-4 shows the
timing of the reset sequence in maximum mode.
4.2.3 Stack Pointer Initialization
The hardware reset sequence does not initialize the stack pointer, so this must be done by
software. If an interrupt were to be accepted after a reset and before the stack pointer (SP) is
initialized, the program counter and status register would not be saved correctly, causing a
program crash. This danger can be avoided by coding the reset routine as explained next.
When the chip comes out of the reset state all interrupts, including NMI, are disabled, so the
instruction at the reset start address is always executed. In the minimum mode, this instruction
should initialize the stack pointer (SP). In the maximum mode, this instruction should be an LDC
instruction initializing the stack page register (TP), and the next instruction should initialize the
stack pointer. Execution of the LDC instruction disables interrupts again, ensuring that the stack
pointer initializing instruction is executed.
H’0000
H’0001
(1) Minimum mode
PC (Upper)
PC (Lower)
Figure 4-2 Reset Vector
86
H’0000
H’0001
H’0002
H’0003
(2) Maximum mode
PC (Upper)
PC (Lower)
Don’t care
CP