HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 141

• Manufacturer Part Number: HD6475328-CP10
• Description: original Hitachi CMOS microcomputer unit (MCU)
• Manufacturer: HITACHI [Hitachi Semiconductor]

Table 6-5 Number of States per Data Transfer
Increment Mode
Source
(SI)
0
0
1
1
Note: Numbers in the table are the number of states.
The values in table 6-5 are calculated from the formula:
N = 26 + 2 SI + 2 DI + M
Where M
The values of M
If the DTC control register information is stored in external RAM, 20 + 4 SI + 4 DI must be
added to the values in table 6-5.
The values given above do not include the time between the occurrence of the interrupt request
and the starting of the DTC. This time includes two states for the interrupt controller to check
priority and a variable wait until the end of the current CPU instruction. At maximum, this time
equals the sum of the values indicated for items No. 1 and 2 in table 6-6.
If the data transfer count is 0 at the end of a data transfer cycle, the number of states from the end
of the data transfer cycle until the first instruction of the user-coded interrupt-handling routine is
executed is the value given for item No. 3 in table 6-6.
M
M
S
D
Byte or word data in on-chip RAM:
Byte data in external RAM or register field:
Word data in external RAM or register field:
: Number of states for reading source data
: Number of states for writing destination data
S
Destina-
tion (DI)
0
1
0
1
and M
S
D
and M
have the following meanings:
D
depend on the data location as follows:
On-Chip RAM
Byte Transfer
31
33
33
35
S
+ M
D
Module or I/O
Register
Word Transfer
34
36
36
38
123
2 states
3 states
6 states
External RAM
Byte Transfer
32
34
34
36
Module or I/O
Register
Word Transfer
38
40
40
42