HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 265

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HD6475328-CP10

Manufacturer Part Number
HD6475328-CP10
Description
original Hitachi CMOS microcomputer unit (MCU)
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
Bit 4—Parity Mode (O/E): In asynchronous mode, when parity is enabled (PE = 1), this bit
selects even or odd parity.
Even parity means that a parity bit is added to the data bits for each character to make the total
number of 1’s even. Odd parity means that the total number of 1’s is made odd.
This bit is ignored when PE = 0 and in the synchronous mode.
Bit 4
O/E
0
1
Bit 3—Stop Bit Length (STOP): This bit selects the number of stop bits. It is ignored in the
synchronous mode.
Bit 3
STOP
0
1
Bit 2—Reserved: This bit cannot be modified and is always read as 1.
Bits 1 and 0—Clock Select 1 and 0 (CKS1 and CKS0): These bits select the internal clock
source when the baud rate generator is clocked from within the H8/532 chip.
Bit 1
CKS1
0
0
1
1
Description
Even parity.
Odd parity.
Description
1 Stop bit.
2 Stop bits.
Bit 0
CKS0
0
1
0
1
Description
ø clock
ø/4 clock
ø/16 clock
ø/64 clock
250
(Initial value)
(Initial value)
(Initial value)

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