HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 208
HD6475328-CP10
Manufacturer Part Number
HD6475328-CP10
Description
original Hitachi CMOS microcomputer unit (MCU)
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
1.HD6475328-CP10.pdf
(459 pages)
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The pulse width of the external clock signal must be at least 1.5·ø clock periods. The counter will
not increment correctly if the pulse width is shorter than 1.5·ø clock periods.
10.4.2 Output Compare Timing
Setting of Output Compare Flags A and B (OCFA and OCFB): The output compare flags are
set to “1” by an internal compare-match signal generated when the FRC value matches the OCRA
or OCRB value. This compare-match signal is generated at the last state in which the two values
match, just before the FRC increments to a new value.
Accordingly, when the FRC and OCR values match, the compare-match signal is not generated
until the next period of the clock source. Figure 10-4 shows the timing of the setting of the output
compare flags.
ø
External clock
source
FRC clock pulse
FRC
ø
FTCI
Figure 10-3 Increment Timing for External Clock Input
Minimum FTCI Pulse Width
N
191
N + 1
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