HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 123

• Manufacturer Part Number: HD6475328-CP10
• Description: original Hitachi CMOS microcomputer unit (MCU)
• Manufacturer: HITACHI [Hitachi Semiconductor]

When the interrupt controller receives one or more interrupt requests, it selects the request with
the highest priority and compares its priority level with the interrupt mask level set in bits I2 to I0
in the CPU status register. If the priority level is higher than the mask level, the interrupt
controller passes the interrupt request to the CPU (or starts the data transfer controller). If the
priority level is lower than the mask level, the interrupt controller leaves the interrupt request
pending until the interrupt mask is altered to a lower level or the interrupt priority is raised.
Similarly, if it receives two interrupt requests with the same priority level, the interrupt controller
determines their priority as explained in table 5-2 and leaves the interrupt request with the lower
priority pending.
5.3.2 Timing of Priority Setting
The interrupt controller requires two system clock (ø) periods to determine the priority level of an
interrupt. Accordingly, when an instruction modifies an instruction priority register, the new
priority does not take effect until after the next instruction has been executed.
5.4 Interrupt Handling Sequence
5.4.1 Interrupt Handling Flow
The interrupt-handling sequence follows the flowchart in figure 5-2. Note that address error, trace
exception, and NMI requests bypass the interrupt controller’s priority decision logic and are
routed directly to the CPU.
1. Interrupt requests are generated by one or more on-chip supporting modules or external
2. The interrupt controller checks the interrupt priorities set in IPRA to IPRD and selects the
3. The interrupt controller compares the priority level of the selected interrupt request with the
4. The interrupt controller checks the corresponding bit (if any) in the data transfer enable
When the data transfer controller is started, the interrupt request is cleared (except for interrupt
requests from the serial communication interface, which are cleared by writing to the TDR or
reading the RDR).
interrupt sources.
interrupt with the highest priority. Interrupts with lower priorities remain pending. Among
interrupts with the same priority level, the interrupt controller determines priority as explained
in table 5-2.
mask level in the CPU status register (bits I2 to I0). If the priority level is equal to or less than
the mask level, the interrupt request remains pending. If the priority level is higher than the
mask level, the interrupt controller accepts the interrupt request and proceeds to the next step.
registers (DTEA to DTED). If this bit is set to “1,” the data transfer controller is started.
Otherwise, the CPU interrupt exception-handling sequence is started.
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