HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 4

• Manufacturer Part Number: HD6475328-CP10
• Description: original Hitachi CMOS microcomputer unit (MCU)
• Manufacturer: HITACHI [Hitachi Semiconductor]

3.6
3.7
3.8
3.9
Section 4 Exception Handling
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
3.5.8 System Control Instructions ······················································································59
3.5.9 Short-Format Instructions ·························································································62
Operating Modes ··················································································································62
3.6.1 Minimum Mode ········································································································62
3.6.2 Maximum Mode ········································································································63
Basic Operational Timing ····································································································63
3.7.1 Overview ···················································································································63
3.7.2 On-Chip Memory Access Cycle ···············································································64
3.7.3 Pin States during On-Chip Memory Access ·····························································65
3.7.4 Register Field Access Cycle (Addresses H'FF80 to H'FFFF) ···································66
3.7.5 Pin States during Register Field Access (Addresses H'FF80 to H'FFFF) ·················67
3.7.6 External Access Cycle ·······························································································68
CPU States ···························································································································69
3.8.1 Overview ···················································································································69
3.8.2 Program Execution State ···························································································71
3.8.3 Exception-Handling State ·························································································71
3.8.4 Bus-Released State ····································································································72
3.8.5 Reset State ·················································································································77
3.8.6 Power-Down State ····································································································77
Programming Notes ·············································································································78
3.9.1 Restriction on Address Location ···············································································78
3.9.2 Note on MULXU Instruction·····················································································79
Overview ······························································································································81
4.1.1 Types of Exception Handling and Their Priority ······················································81
4.1.2 Hardware Exception-Handling Sequence ·································································82
4.1.3 Exception Factors and Vector Table ··········································································82
Reset ····································································································································85
4.2.1 Overview ···················································································································85
4.2.2 Reset Sequence ·········································································································85
4.2.3 Stack Pointer Initialization ························································································86
Address Error ·······················································································································89
4.3.1 Illegal Instruction Prefetch ························································································89
4.3.2 Word Data Access at Odd Address ···········································································89
4.3.3 Off-Chip Address Access in Single-Chip Mode ·······················································89
Trace ····································································································································90
Interrupts ······························································································································90
Invalid Instruction ················································································································92
Trap Instructions and Zero Divide ·······················································································92
Cases in Which Exception Handling is Deferred ·································································92