HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 452

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HD6475328-CP10

Manufacturer Part Number
HD6475328-CP10
Description
original Hitachi CMOS microcomputer unit (MCU)
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
4. Mode 4
Figures E-7 and E-8 show how the pin states change when the RES pin goes Low during external
memory access in mode 4.
As soon as RES goes Low, all ports are initialized to the input (high-impedance) state. The AS,
DS, RD, and WR signals all go High. The data bus (D
state. Pins P5
bus are initialized as input ports.
Pins A
Low state of the RES pin is sampled. Pins A
High.
The clock output pins P1
RES pin is sampled. Both pins are initialized to the output state.
7
to A
0
7
of the address bus and the R/W signal are initialized 1.5 ø clock periods after the
/A
15
to P5
0
0
/ø and P1
/A
8
of the address bus and pins P6
1
/E are initialized 0.5 ø clock periods after the Low state of the
7
to A
443
0
are made Low. The R/W signal is made
7
to D
0
3
) is placed in the high-impedance
/A
19
to P6
0
/A
16
of the page address

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