HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 82

• Manufacturer Part Number: HD6475328-CP10
• Description: original Hitachi CMOS microcomputer unit (MCU)
• Manufacturer: HITACHI [Hitachi Semiconductor]

3.6.2 Maximum Mode
In the maximum mode the page registers are valid, expanding the maximum address space to 1M
byte.
The address space is divided into 64k-byte pages. The pages are separate; it is not possible to
move continuously across a page boundary.
It is possible to move from one page to another with branching instructions (PJMP, PJSR, PRTS,
PRTD). The TRAPA instruction and branches to interrupt-handling routines can also jump across
page boundaries. It is not necessary for a program to be contained in a single 64k-byte page.
When data access crosses a page boundary, the program must rewrite the page register before it
can access the data in the next page.
For further information on the operating modes, see section 2, “MCU Operating Modes and
Address Space.”
3.7 Basic Operational Timing
3.7.1 Overview
The CPU operates on a system clock (ø) which is created by dividing an oscillator frequency
(fosc) by two. One period of the system clock is referred to as a “state.” The CPU accesses
memory in a cycle consisting of 2 or 3 states. The CPU uses different methods to access on-chip
memory, the on-chip register field, and external devices.
Access to On-Chip Memory (RAM, ROM): For maximum speed, access to on-chip memory
(RAM, ROM) is performed in two states, using a 16-bit-wide data bus.
Figure 3-6 shows the on-chip memory access cycle. Figure 3-7 indicates the pin states. The bus
control signals output from the H8/532 chip go to the nonactive state during the access.
Access to On-Chip Register Field (Addresses H'FF80 to H'FFFF): The access cycle consists
of three states. The data bus is 8 bits wide.
Figure 3-8 shows the on-chip supporting module access cycle. Figure 3-9 indicates the pin states.
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