HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 13

• Manufacturer Part Number: HD6475328-CP10
• Description: original Hitachi CMOS microcomputer unit (MCU)
• Manufacturer: HITACHI [Hitachi Semiconductor]

Figures
1-1
1-2
1-3
1-4
2-1
2-2
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10 (a) External Access Cycle (Read Access) ·············································································68
3-10 (b) External Access Cycle (Write Access) ············································································69
3-11
3-12
3-13
3-14
3-15
4-1
4-2
4-3
4-4
4-5
5-1
5-2
5-3 (a) Stack before and after Interrupt Exception-Handling (Minimum Mode) ······················107
5-3 (b) Stack before and after Interrupt Exception-Handling (Maximum Mode) ·····················108
5-4
5-5
6-1
6-2
6-3
6-4
6-5
6-6
7-1
Block Diagram ···················································································································4
Pin Arrangement (CP-84, Top View) ·················································································5
Pin Arrangement (CG-84, Top View) ················································································6
Pin Arrangement (FP-80A, Top View) ··············································································7
Address Space in Each Mode ··························································································26
Map of Page 0 ··················································································································28
CPU Operating Modes ·····································································································32
Registers in the CPU ········································································································33
Stack Pointer ····················································································································34
Combinations of Page Registers with Other Registers ····················································38
Short Absolute Addressing Mode and Base Register ······················································39
On-Chip Memory Access Timing ····················································································64
Pin States during Access to On-Chip Memory ································································65
Register Field Access Timing ··························································································66
Pin States during Register Field Access ··········································································67
Operating States ···············································································································70
State Transitions ··············································································································71
Bus-Right Release Cycle (During On-chip Memory Access Cycle) ·······························73
Bus-Right Release Cycle (During External Access Cycle) ·············································74
Bus-Right Release Cycle (During Internal CPU Operation) ···········································75
Types of Factors Causing Exception Handling ································································83
Reset Vector ·····················································································································86
Reset Sequence (Minimum Mode, On-Chip Memory) ···················································87
Reset Sequence (Maximum Mode, External Memory) ···················································88
Interrupt Sources (and Number of Interrupt Types) ························································91
Interrupt Controller Block Diagram ················································································98
Interrupt Handling Flowchart ························································································106
Interrupt Sequence (Minimum Mode, On-Chip Memory) ············································109
Interrupt Sequence (Maximum Mode, External Memory) ············································110
Block Diagram of Data Transfer Controller ··································································114
Flowchart of Data Transfer Cycle ··················································································119
DTC Vector Table ··········································································································120
DTC Vector Table Entry ································································································121
Order of Register Information ·······················································································122
Use of DTC to Receive Data via Serial Communication Interface ·······························126
Block Diagram of Wait-State Controller ·······································································128