HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 284

• Manufacturer Part Number: HD6475328-CP10
• Description: original Hitachi CMOS microcomputer unit (MCU)
• Manufacturer: HITACHI [Hitachi Semiconductor]

Table 14-9 SCI Interrupts
Interrupt
ERI
RXI
TXI
The TXI and RXI interrupts can be served by the data transfer controller (DTC) to have a data
transfer performed. When the DTC serves one of these interrupts, it clears the TDRE or RDRF bit
to 0 under the following conditions, which differ between the two bits.
When invoked by a TXI request, if the DTC writes to the TDR, it automatically clears the TDRE
bit to 0. When invoked by an RXI request, if the DTC reads from the RDR, it automatically clears
the RDRF bit to 0.
See section 6, “Data Transfer Controller” for further information on the DTC.
14.5 Application Notes
Application programmers should note the following features of the SCI.
1. TDR Write: The TDRE bit in the SSR is simply a flag that indicates that the TDR contents
2. Multiple Receive Errors: Table 14-10 lists the values of flag bits in the SSR when multiple
have been transferred to the TSR. The TDR contents can be rewritten regardless of the TDRE
value. If a new byte is written in the TDR while the TDRE bit is 0, before the old TDR
contents have been moved into the TSR, the old byte will be lost. Normally, software should
check that the TDRE bit is set to 1 before writing to the TDR.
receive errors occur, and indicates whether the RSR contents are transferred to the RDR.
Description
Receive-error interrupt, requested when
ORER, FER, or PER is set.
Receive-end interrupt, requested when
RDRF is set.
Transmit-end interrupt, requested when
TDRE is set.
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DTC Service
Available?
No
Yes
Yes
Priority
High
Low