HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 381
HD6475328-CP10
Manufacturer Part Number
HD6475328-CP10
Description
original Hitachi CMOS microcomputer unit (MCU)
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
1.HD6475328-CP10.pdf
(459 pages)
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B.2 Register Descriptions
Acronym of the register
Bit
numbers
Initial bit
values
Type of access permitted
R
W
R/W Both read and write
Read only
Write only
SYSCR1—System Control Register 1
Bit
Initial value
Read/Write
Register name
—
—
7
1
IRQ
Interrupt Request 1 Enable
R/W
0
1
6
0
1
E
P1
P1
6
6
is an I/O port; IRQ
is the IRQ
IRQ
R/W
Interrupt Request 0 Enable
0
1
5
0
0
E
P1
P1
5
5
1
NMIEG
is an I/O port; IRQ
is the IRQ
input pin.
R/W
Nonmaskable Interrupt Edge
0
1
4
0
372
Address to which the
register is mapped
An NMI request is generated on the falling edge of the NMI pin input.
An NMI request is generated on the rising edge of the NMI pin input.
1
input is disabled.
0
BRLE
R/W
input pin.
H'FEFC
Bus Release Enable
3
0
0
1
P1
P1
0
2
2
input is disabled.
and P1
is the BACK output pin. P1
—
—
2
1
3
are I/O ports.
—
—
1
1
Functions of the bit settings
—
—
3
Port 1
0
1
Name of the on-chip
supporting module
is the BREQ input pin.
Full name of the bit
Names of the
bits.
Dashes (—)
indicate
reserved bits.
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