HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 441

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HD6475328-CP10

Manufacturer Part Number
HD6475328-CP10
Description
original Hitachi CMOS microcomputer unit (MCU)
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
Table E-1 Port State (cont)
H: “High” = High level
L: “Low” = Low level
T: High Impedance
keep: If DDR = 0 and DR = 1 in port 5 and 6, Pull-up MOS holds on-state.
Notes:
*1 8 Bit Timer is reset, so P1
*2 On-chip supporting modules are reset. So these pins become input or output ports controlled
*3 BREQ can be accepted and BACK goes LOW.
*4 BACK outputs LOW.
*5 The pins programmed as address bus output LOW and others programmed as input are at the
*6 If DDR = 0 and DR = 1, the pull-up MOS’s keep ON state.
Port
Pin Name
P6
A
P7
P8
P9
19
3
7
7
7
goes to the high impedance state when it is programmed as BACK output.
by DDR and DR.
high impedance state.
If DDR = 0 and DR = 1, the pull-up MOS’s keep ON state.
to A
to P6
to P7
to P8
to P9
16
0
0
0
0
Mode Reset
1
2
3
4
7
1
2
3
4
7
1
2
3
4
7
1
2
3
4
7
T
L
T
T
T
T
7
becomes input or output port controlled by DDR and DR. Also P1
Hardware
Standby
Mode
T
T
T
T
Software
Standby mode Sleep Mode
T
T
keep
keep
T
keep
keep
*6
*2
*2
432
L
*5
keep
keep
T
keep
keep
T
T
---
keep
T
keep
Bus-right
Release Mode State (Normal Operation)
keep
*6
Program Execution
A
Address/Input port
Input/Output port
Input port
Input port
Input/Output port
Input/Output port
19
to A
16
2

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