HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 202

• Manufacturer Part Number: HD6475328-CP10
• Description: original Hitachi CMOS microcomputer unit (MCU)
• Manufacturer: HITACHI [Hitachi Semiconductor]

Bit
Initial value
Read/Write
Bit 2
OEA
0
1
Bits 1 and 0—Clock Select (CKS1 and CKS0): These bits select external clock input or one of
three internal clock sources for the FRC. External clock pulses are counted on the rising edge.
Bit 1
CKS1
0
0
1
1
* Output enable bit (bit 3) must be cleared to “0.”
10.2.5 Timer Control/Status Register (TCSR)
The TCSR is an 8-bit readable and partially writable* register that selects the input capture edge
and output compare levels, and specifies whether to clear the counter on compare-match A. It also
contains four status flags.
The TCSR is initialized to H'00 at a reset and in the standby modes.
* Software can write a “0” in bits 7 to 4 to clear the flags, but cannot write a “1” in these bits.
Bit 7—Input Capture Flag (ICF): This status flag is set to “1” to indicate an input capture
event. It signifies that the FRC value has been copied to the ICR.
Description
Output compare A output is disabled.
Output compare A output is enabled.
Bit 0
CKS0
0
1
0
1
R/(W)*
ICF
7
0
Description
Internal clock source (ø/4)
Internal clock source (ø/8)
Internal clock source (ø/32)
External clock source (counted on the rising edge)*
R/(W)*
OCFB
6
0
R/(W)*
OCFA
5
0
R/(W)*
185
OVF
4
0
(Initial value)
(Initial value)
OLVLB
R/W
3
0
OLVLA
R/W
2
0
IEDG
R/W
1
0
CCLRA
R/W
0
0