HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 130

• Manufacturer Part Number: HD6475328-CP10
• Description: original Hitachi CMOS microcomputer unit (MCU)
• Manufacturer: HITACHI [Hitachi Semiconductor]

5.6 Interrupt Response Time
Table 5-4 indicates the number of states that may elapse between the generation of an interrupt
request and the execution of the first instruction of the interrupt-handling routine, assuming that
the interrupt is not masked and not preempted by a higher-priority interrupt. Since word access is
performed to on-chip memory areas, fastest interrupt service can be obtained by placing the
program in on-chip ROM and the stack in on-chip RAM.
Table 5-4 Number of States before Interrupt Service
No.
1
2
3
Total
Note: m: Number of wait states inserted in external memory access.
Reason for Wait
Interrupt priority decision and comparison with
mask level in CPU status register
Maximum number of
states to completion
of current instruction
Saving of PC and SR
or PC, CP, and SR
and instruction prefetch
Stack is in
on-chip RAM
Stack is in
external RAM
Values in parentheses are for the LDM instruction.
Instruction is in on-chip
memory
Instruction is in external
memory
Stack is in on-chip RAM
Stack is in external memory 28 + 6m
Instruction is in on-chip
memory
Instruction is in external
memory
Instruction is in on-chip
memory
Instruction is in external
memory
111
Minimum Mode
2 states
x
(x = 38 for LDM instruction specifying
all registers)
y
(y = 74 + 16m for LDM instruction
specifying all registers)
16
18 + x
(56)
18 + y
(92 + 16m)
30 + 6m + x
(68 + 6m)
30 + 6m + y
(104 + 22m)
Number of States
Maximum Mode
21
41 + 10m
23 + x
(61)
23 + y
(97 + 16m)
43 + 10m + x
(81 + 10m)
43 + 10m + y
(117 + 26m)