HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 278

• Manufacturer Part Number: HD6475328-CP10
• Description: original Hitachi CMOS microcomputer unit (MCU)
• Manufacturer: HITACHI [Hitachi Semiconductor]

(4) The first byte of transmit data is transferred from the TDR to the TSR and sent in the
(5) Transfer of the transmit data from the TDR to the TSR makes the TDR empty, so the
• Data Reception: The procedure for receiving data is as follows.
(1) Set up the desired receiving conditions in the SMR, SCR, and BRR.
(2) Set the RE bit in the SCR to 1.
(3) The SCI synchronizes with the incoming data by detecting the start bit, and places the
(4) When a complete frame has been received, the SCI transfers the received data to the RDR
(5) The RDRF bit is cleared to 0 when the CPU reads the SSR, then writes a 0 in the RDRF
When a frame is not received correctly, a receive error occurs. There are three types of receive
errors, listed in table 14-8.
If a receive error occurs, the RDRF bit in the SSR is not set to 1. The corresponding error flag
is set to 1 instead. If the RIE bit in the SCR is set to 1, a receive-error interrupt (ERI) is
requested.
designated format as follows.
i)
ii) Transmit data (seven or eight bits, starting from bit 0)
iii) Parity bit (odd or even parity bit, or no parity bit)
iv) Stop bit (one or two consecutive 1 bits)
TDRE bit is set to 1.
If the TIE bit is set to 1, a transmit-end interrupt (TXI) is requested.
When the transmit function is enabled but the TDR is empty (TDRE = 1), the output at the
TXD pin is held at 1 until the TDRE bit is cleared to 0.
The RXD pin will automatically be switched to input and the SCI is ready to receive data.
received bits in the RSR. At the end of the data, the SCI checks that the stop bit is 1.
If the stop bit length is 2 bits, in ZTAT versions the SCI checks that both bits are 1, but in
masked-ROM versions, only the first bit is checked.
so that it can be read. If the character length is 7 bits, the most significant bit of the RDR
is cleared to 0. At the same time, the SCI sets the RDRF bit in the SSR to 1. If the RIE bit
is set to 1, a receive-end interrupt (RXI) is requested.
bit, or when the RDR is read by the data transfer controller (DTC). The RDR is then ready
to receive the next character from the RSR.
Start bit (one 0 bit)
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