HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 178

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HD6475328-CP10

Manufacturer Part Number
HD6475328-CP10
Description
original Hitachi CMOS microcomputer unit (MCU)
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
9.6.4 Built-In MOS Pull-Up
The MOS input pull-ups of port 5 are turned on by clearing the corresponding bit in P5DDR to
“0” and writing a “1” in P5DR. These pull-ups are turned off at a reset and in the hardware
standby mode. Table 9-9 indicates the status of the MOS pull-ups in various modes.
Table 9-9 Status of MOS Pull-Ups for Port 5
Mode
1
2
3
4
7
* Including the software standby mode.
Notation:
OFF:
ON/OFF:
Note on Usage of MOS Pull-Ups
If the bit manipulation instructions listed below are executed on input/output ports 5 and 6 which
have selectable MOS pull-ups, the logic levels at input pins will be transferred to the DR latches,
causing the MOS pull-ups to be unintentionally switched on or off.
This can occur with the following bit manipulation instructions: BSET, BCLR, BNOT
(1)
Specific Example (BSET Instruction): An example will be shown in which the BSET
instruction is executed for port 5 under the following conditions:
P5
P5
P5
The intended purpose of this BSET instruction is to switch the output level at P5
to high.
7
6
5
Reset
OFF
:
:
– P5
The MOS pull-up is always off.
The MOS pull-up is on when P5DDR = 0 and P5DR = 1, and off otherwise.
0
: Output pins, low
Input pin, low, MOS pull-up transistor on
Input pin, high, MOS pull-up transistor off
Hardware Standby Mode
OFF
161
Other Operating States*
OFF
ON/OFF
OFF
ON/OFF
0
from low

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