HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 127

• Manufacturer Part Number: HD6475328-CP10
• Description: original Hitachi CMOS microcomputer unit (MCU)
• Manufacturer: HITACHI [Hitachi Semiconductor]

5.4.3 Timing of Interrupt Exception-Handling Sequence
Figure 5-4 shows the timing of the exception-handling sequence for an interrupt when the
program area and stack area are both in on-chip memory and the user-coded interrupt handling
routine starts at an even address.
5.5 Interrupts During Operation of the Data Transfer Controller
If an interrupt is requested during a DTC data transfer cycle, the interrupt is not accepted until the
data transfer cycle has been completed and the next instruction has been executed. This is true
even if the interrupt is an NMI. An example is shown below.
(Example)
Address
2m – 6
2m – 5
2m – 4
2m – 3
2m – 2
2m – 1
2m
Notes:
1. PC: The address of the next instruction to be executed is saved.
2. Register saving and restoring must start at an even address (e.g 2m).
ADD.W
MOV.W
ADD.W
Figure 5-3 (b) Stack before and after Interrupt Exception-Handling
Stack area
R2, R0
R0, @H'FF00
@H' FF02,R0
(Before)
Program flow
(Maximum Mode)
DTC interrupt request
SP
Save to stack
108
After data transfer cycle, CPU executes next
instruction before starting exception handling
Data transfer cycle request
Address
2m – 6
2m – 5
2m – 4
2m – 3
2m – 2
2m – 1
2m
To NMI exception handling sequence
Upper 8 bits of SR
Lower 8 bits of SR
Upper 8 bits of PC
Lower 8 bits of PC
Don’t care
(After)
CP
NMI interrupt
SP