HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 58

• Manufacturer Part Number: HD6475328-CP10
• Description: original Hitachi CMOS microcomputer unit (MCU)
• Manufacturer: HITACHI [Hitachi Semiconductor]

are saved and restored in exception handling.
Data Page Register (DP): The data page register combines with general registers R0 to R3 to
generate a 24-bit effective address. The data page register contains the upper 8 bits of the address.
It is used to calculate effective addresses in the register indirect addressing mode using R0 to R3,
and in the 16-bit absolute addressing mode (@aa:16).
The data page register is rewritten by the LDC instruction.
Extended Page Register (EP): The extended page register combines with general register R4 or
R5 to generate a 24-bit operand address. The extended page register contains the upper 8 bits of
the address. It is used to calculate effective addresses in the register indirect addressing mode
using R4 or R5.
The extended page can be used as an additional data page.
Stack Page Register (TP): The stack page register combines with R6 (FP) or R7 (SP) to
generate a 24-bit stack address. The stack page register contains the upper 8 bits of the address. It
is used to calculate effective addresses in the register indirect addressing mode using R6 or R7, in
exception handling, and subroutine calls.
Base Register (BR): This 8-bit register stores the base address used in the short absolute
addressing mode (@aa:8). In this addressing mode a 16-bit effective address in page 0 is
generated by using the contents of the base register as the upper 8 bits and an address given in the
instruction code as the lower 8 bits. See figure 3-5.
In the short absolute addressing mode the address is always located in page 0.
8 Bits
8 Bits
BR
@ aa : 8
16 Bits (effective address)
Figure 3-5 Short Absolute Addressing Mode and Base Register
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