HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 120

• Manufacturer Part Number: HD6475328-CP10
• Description: original Hitachi CMOS microcomputer unit (MCU)
• Manufacturer: HITACHI [Hitachi Semiconductor]

In the CPU interrupt-handling sequence for IRQ
“0,” and the interrupt mask level is set to the value in the lower four bits of IPRA.
Coding Examples:
To enable IRQ
To assign priority level 7 to IRQ
To have IRQ
5.2.2 Internal Interrupts
Nineteen types of internal interrupts can be requested by the on-chip supporting modules. Each
interrupt is separately vectored in the exception vector table, so it is not necessary for the user-
coded interrupt handler routine to determine which type of interrupt has occurred.
Each of the internal interrupts can be enabled or disabled by setting or clearing an enable bit in the
control register of the on-chip supporting module.
An interrupt priority level from 7 to 0 can be assigned to each on-chip supporting module by
setting interrupt priority registers B to D. Within each module, different interrupts have a fixed
priority order. For most of these interrupts, values set in data transfer enable registers B to D can
select whether to have the interrupt served by the CPU or the data transfer controller.
In the CPU interrupt-handling sequence, the T bit of the CPU status register is cleared to “0,” and
the interrupt mask level in bits I2 to I0 is set to the value in the IPR.
5.2.3 Interrupt Vector Table
Table 5-2 lists the addresses of the exception vector table entries for each interrupt, and explains
how their priority is determined. For the on-chip supporting modules, the priority level set in the
interrupt priority register applies to the module as a whole: all interrupts from that module have
the same priority level. A separate priority order is established among interrupts from the same
module. If the same priority level is assigned to two or more modules and two interrupts are
requested simultaneously from these modules, they are served in the priority order indicated in the
rightmost column in table 5-2.
A reset clears the interrupt priority registers so that all interrupts except NMI start with priority
level 0, meaning that they are unconditionally masked.
1
start the DTC:
1
to be requested by IRQ
0
and level 5 to IRQ
1
input:
101
1
, the T bit of the CPU status register is cleared to
1
:
BSET.B #6, @H'FFFC
MOV.B #75, @H'FFF0
BSET.B #0, @H'FFF4