CD2231 Intel Corporation, CD2231 Datasheet - Page 118

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CD2231

Manufacturer Part Number
CD2231
Description
CD2231 Intelligent Two-channel Lan And Wan Communications Controller
Manufacturer
Intel Corporation
Datasheet
CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
8.4.3.1
8.4.3.2
118
Register Name: CSR
Register Description: Channel Status
Default Value: x’00
Access: Byte Read/Write
Register Name: CSR
Register Description: Channel Status
Default Value: x’00
Access: Byte Read/Write
RxEn
RxEn
Bit 7
Bit 7
CSR — HDLC Mode
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CSR — Async Mode
If the host determines that a flow control state is inappropriate, it can be cleared by enabling or
disabling the transmitter or receiver by CCR command.
RxFlag
RxFloff
Bit 6
Bit 6
Receiver enable
0 = Receiver is disabled
1 = Receiver is enabled
Rx flag
0 = Currently not receiving flag/sync
1 = Currently receiving flag/sync
Rx frame
0 = Currently not receiving frame
1 = Currently receiving frame
Rx mark
0 = Currently not receiving continuous mark
1 = Currently receiving continuous mark
Transmitter enable
0 = Transmitter is disabled
1 = Transmitter is enabled
Tx flag
0 = Currently not transmitting flag
1 = Currently transmitting flag
Tx frame
0 = Currently not transmitting frame
1 = Currently transmitting frame
Tx mark
0 = Currently not transmitting continuous ones
1 = Currently transmitting continuous ones
RxFrame
RxFlon
Bit 5
Bit 5
RxMark
Bit 4
Bit 4
0
TxEn
TxEn
Bit 3
Bit 3
TxFloff
TxFlag
Bit 2
Bit 2
Motorola Hex Address: x’1A
Motorola Hex Address: x’1A
TxFrame
TxFlon
Bit 1
Bit 1
Intel Hex Address: x’19
Intel Hex Address: x’19
Datasheet
TxMark
Bit 0
Bit 0
0

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