CD2231

Manufacturer Part NumberCD2231
DescriptionCD2231 Intelligent Two-channel Lan And Wan Communications Controller
ManufacturerIntel Corporation
CD2231 datasheet
 


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
Page 171
172
Page 172
173
Page 173
174
Page 174
175
Page 175
176
Page 176
177
Page 177
178
Page 178
Page 171/178

Download datasheet (3Mb)Embed
PrevNext
FCT (flow control transparency) mode 98,
103
Flag Hunt mode 68
Flag mode 67, 68
HDLC mode 90, 92, 96, 118, 127
High-Impedance mode 18
Idle mode 96
Idle-in Mark mode 96
Local Loopback mode 112
Mark mode 67, 68
MNP4 mode 95
MNP4/SLIP mode 93
Parity mode 91
Protocol mode 89
Receive Transfer mode 89
Remote Loopback mode 93, 94
SLIP mode 97, 129
SLIP/MNP4 mode 116, 120
Syn/Flag Hunt mode 115
Synchronous mode 96
Transmit Transfer mode 89
XON mode 92
multi–CD2430 systems 40
O
operations
BGR 57
DMA 42
DPLL 57
FIFO and timer 41
receive FIFO 41
transmit FIFO 41
ordering information example 168
P
package specifications 167
Parity mode 91
pin information
descriptions 16
diagram 15
functions 16
programming examples 84
Datasheet
programming the PILR registers 39
Protocol mode 89
protocol processing 67
R
read cycle, host 35
receive buffer interrupts 55
receive bus errors 56
receive DMA interrupt service routine 86
receive DMA transfer 50
receive FIFO operation 41
receive time-out 56
Receive Transfer mode 89
receiver
A and B buffers 50
fixed operations 72
options 72
register definitions 24
register descriptions, detailed 88
register table 20
registers
Bit Rate and Clock Option registers
RBPR 21, 27, 110
RCOR 21, 28, 110
TBPR 21, 28, 111
TCOR 21, 28, 112
Channel Command and Status registers
CCR 22, 28, 113
CSR 22, 28, 117
MSVR-DTR 22, 29, 121
MSVR-RTS 22, 29, 121
STCR 22, 28, 115
DMA Receive registers
ARBADRL 23, 32, 141
ARBADRU 23, 32, 142
ARBCNT 23, 32, 143
ARBSTS 23, 32, 143
BRBADRL 23, 32, 142
BRBADRU 23, 32, 142
BRBCNT 23, 32, 143
BRBSTS 23, 32, 144
RCBADRL 23, 32, 144
171