CD2231

Manufacturer Part NumberCD2231
DescriptionCD2231 Intelligent Two-channel Lan And Wan Communications Controller
ManufacturerIntel Corporation
CD2231 datasheet
 


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
Page 141
142
Page 142
143
Page 143
144
Page 144
145
Page 145
146
Page 146
147
Page 147
148
Page 148
149
Page 149
150
Page 150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
Page 144/178

Download datasheet (3Mb)Embed
PrevNext
CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
8.6.4.8
B Receive Buffer Status (BRBSTS)
Register Name: BRBSTS
Register Description: Receive Buffer ‘B’ Status
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Berr
EOF
EOB
These registers contain the current status of associated receive buffers and enable the buffers to be
passed between the host and CD2231.
Bit 7
Bus error (set by the CD2231 and cleared by the host CPU)
0 = No bus error
1 = Bus error occurred on the last transfer; the suspect address is available in
RCBADR.
Bit 6
End of frame (set by the CD2231 and cleared by the host CPU)
0 = This buffer does not terminate a frame.
1 = This buffer terminates a frame.
Bit 5
Buffer complete (set by the CD2231 and cleared by the host CPU)
0 = Buffer not complete.
1 = Buffer complete.
Bits 4:1
Reserved – must be ‘0’.
Bit 0
Ownership of the transfer buffer (set by the host CPU and cleared by the CD2231)
0 = Buffer not free to be used by CD2231.
1 = Buffer free to be used by CD2231.
When the Buffer Complete bit is set by the CD2231, the buffer is free for the host to process.
(RBCNT information is updated to the number of bytes available in the buffer, and a new buffer
can be allocated.)
8.6.4.9
Receive Current Buffer Address Register — Lower (RCBADRL)
Register Name: RCBADRL
Register Description: Current Receive Buffer Address, lower word
Default Value: x’0000
Access: Word Read Only
Bit 15
Bit 14
Bit 13
Bit 7
Bit 6
Bit 5
144
Bit 4
Bit 3
0
0
Bit 12
Bit 11
Binary address value, 32-bit address, bits 15:8
Bit 4
Bit 3
Binary address value, 32-bit address, bits 7:0
Intel Hex Address: x’4D
Motorola Hex Address: x’4E
Bit 2
Bit 1
Bit 0
0
0
2231own
Intel Hex Address: x’3C
Motorola Hex Address: x’3E
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Datasheet