CD2231

Manufacturer Part NumberCD2231
DescriptionCD2231 Intelligent Two-channel Lan And Wan Communications Controller
ManufacturerIntel Corporation
CD2231 datasheet
 
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Intelligent Two-Channel LAN and WAN Communications Controller — CD2231
During an interrupt service routine, the host can use this register to provide a binary timer value to
one of the timers (Sync modes only), as detailed in the Modem End of Interrupt register. The host
can only load one of the two timers in each interrupt service routine.
8.5.4.4
Modem End of Interrupt Register (MEOIR)
Register Name: MEOIR
Register Description: Modem End of Interrupt
Default Value: x’00
Access: Byte Write only
Bit 7
Bit 6
Bit 5
0
0
SetTm2
Bits 7:6
Reserved – must be ‘0’.
Bit 5
Set General Timer 2 in Synchronous modes
0 = do not set General Timer 2.
1 = load the value, provided in MISR, to General Timer 2.
Bit 4
Set General Timer 1 in Synchronous modes
0 = do not set General Timer 1.
1 = load the value, provided in MISR, to the high byte of General Timer 1.
At the end of an interrupt service routine, the user can set the timer by setting a timer
value in the Modem Interrupt Status register. When the timer reaches ‘0’, the
CD2231 generates a modem/timer group interrupt to the host.
Bits 3:0
Reserved – must be ‘0’.
8.6
DMA Registers
8.6.1
DMA Mode Register (DMR)
Register Name: DMR
Register Description: DMA Mode
Default Value: x’00
Access: Byte Write only
Bit 7
Bit 6
Bit 5
EnSync
0
0
This register is write only. No misoperation occurs if the register is read, but the read value is not
consistent.
Bit 7
Internal DTACK synchronization enable. If external synchronization of DTACK*
with BUSCLK is not provided, an internal synchronization can be enabled by setting
this bit (Revision D and later).
Bits 6:4
Reserved – must be ‘0’.
Datasheet
Bit 4
Bit 3
Bit 2
SetTm1
0
0
Bit 4
Bit 3
Bit 2
0
ByteDMA
0
Intel Hex Address: x’85
Motorola Hex Address: x’86
Bit 1
Bit 0
0
0
Intel Hex Address: x’F4
Motorola Hex Address: x’F6
Bit 1
Bit 0
0
0
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