CD2231 Intel Corporation, CD2231 Datasheet - Page 64
Manufacturer Part Number
CD2231 Intelligent Two-channel Lan And Wan Communications Controller
CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
Data Clock Selection Using External Clock
To demultiplex the A/D[15:0] bus into separate address and data buses, external buffers and latches
are required. To reduce external circuitry, these external devices can be shared in multi–
CD1400 applications. The common control lines (ADLD*, AEN*, DATDIR*, DATEN*) to
the external devices are wire-OR’ed together. These pins are tristate, not open collector, but an
external pull-up resistor (2.2–5.0 k¾) must be connected to each line to ensure logic 1 when no
CD1400 is a bus master.
When no higher-priority alternate bus masters are present, a daisy-chain priority scheme can be
implemented by wire OR’ing BR* and BGACK* and connecting directly to the 680X0. The
680X0 BG* signal is then connected to the first device in the chain and daisy-chained to the
remaining devices. A lower-priority bus master can then be connected at the end of the chain.
If a higher-priority bus master is present, the BG* signal must be qualified before being passed into
the highest priority CD1400. If a priority encoded scheme is required, the BR* signals must be
prioritized externally and BG* signals routed to individual devices.
Clock = 33 MHz