CD2231

Manufacturer Part NumberCD2231
DescriptionCD2231 Intelligent Two-channel Lan And Wan Communications Controller
ManufacturerIntel Corporation
CD2231 datasheet
 
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Page 64/178

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CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
Table 9.
Data Clock Selection Using External Clock
Bit Rate
50
110
150
300
600
1200
2400
3600
4800
7200
9600
19200
38400
56000
64000
76800
115200
128000
5.6
Hardware Configurations
To demultiplex the A/D[15:0] bus into separate address and data buses, external buffers and latches
are required. To reduce external circuitry, these external devices can be shared in multi–
CD1400 applications. The common control lines (ADLD*, AEN*, DATDIR*, DATEN*) to
the external devices are wire-OR’ed together. These pins are tristate, not open collector, but an
external pull-up resistor (2.2–5.0 k¾) must be connected to each line to ensure logic 1 when no
CD1400 is a bus master.
When no higher-priority alternate bus masters are present, a daisy-chain priority scheme can be
implemented by wire OR’ing BR* and BGACK* and connecting directly to the 680X0. The
680X0 BG* signal is then connected to the first device in the chain and daisy-chained to the
remaining devices. A lower-priority bus master can then be connected at the end of the chain.
If a higher-priority bus master is present, the BG* signal must be qualified before being passed into
the highest priority CD1400. If a priority encoded scheme is required, the BR* signals must be
prioritized externally and BG* signals routed to individual devices.
64
External Clock
Divisor (hex)
Frequency
Clock = 33 MHz
9.765 kHz
c2
9.765 kHz
57
9.765 kHz
40
39.062 kHz
81
39.062 kHz
40
156.250 kHz
81
156.250 kHz
40
625.00 kHz
625.00 kHz
81
1.250 MHz
ac
1.250 MHz
81
1.250 MHz
40
1.250 MHz
1.250 MHz
15
1.250 MHz
12
1.250 MHz
2.00 MHz
10
2.00 MHz
ef
1f
0f
0f
Datasheet