CD2231

Manufacturer Part NumberCD2231
DescriptionCD2231 Intelligent Two-channel Lan And Wan Communications Controller
ManufacturerIntel Corporation
CD2231 datasheet
 


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CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
8.2.3
Channel Option Register 2 (COR2)
8.2.3.1
COR2 — HDLC Mode
Register Name: COR2
Register Description: Channel Option Register 2
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
0
FCSApd
0
Bit 7
Reserved – must be ‘0’.
Bit 6
FCS append
0 = Receive CRC is not passed to the host at end of frame
1 = Receive CRC is passed to the host at end of frame
Bit 5
Reserved – must be ‘0’.
Bit 4
CRCNinv
0 = CRC is transmitted inverted (that is, CRC V.41)
1 = CRC is not transmitted inverted (that is, CRC-16)
Bit 3
Reserved – must be ‘0’.
Bit 2
RTS automatic output enable
When set, if the channel is enabled, the CD2231 automatically asserts the RTS* out-
put when it has characters to send. When Idle-in Mark mode is selected, RTS* is
asserted prior to opening flags and remains asserted until after a closing flag has been
transmitted.
Bit 1
CTS automatic enable
Enables CTS* input to be used as the automatic transmitter enable/disable. If
enabled, the CTS input is checked before frame transmission starts.
Bit 0
DSR Automatic Enable
Enable the DSR* input as the automatic receiver enable/disable. If enabled, DSR*
is checked at the beginning of each received frame.
8.2.3.2
Asynchronous / Async-HDLC / PPP Mode
Register Name: COR2
Register Description: Channel Option Register 2
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
IXM
TxIBE
0
Bit 7
IXM – Implied XON mode
IXM has meaning only when TxIBE is set.
If transmission has been stopped due to a received XOFF character, and:
92
Bit 4
Bit 3
Bit 2
CRCNinv
0
RtsAO
Bit 4
Bit 3
Bit 2
0
RLM
RtsAO
Intel Hex Address: x’14
Motorola Hex Address: x’17
Bit 1
Bit 0
CtsAE
DsrAE
Intel Hex Address: x’14
Motorola Hex Address: x’17
Bit 1
Bit 0
CtsAE
DsrAE
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