CD2231

Manufacturer Part NumberCD2231
DescriptionCD2231 Intelligent Two-channel Lan And Wan Communications Controller
ManufacturerIntel Corporation
CD2231 datasheet
 


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
Page 141
142
Page 142
143
Page 143
144
Page 144
145
Page 145
146
Page 146
147
Page 147
148
Page 148
149
Page 149
150
Page 150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
Page 148/178

Download datasheet (3Mb)Embed
PrevNext
CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
B Transmit Buffer Status (BTBSTS) — Async-HDLC/PPP Mode
Register Name: BTBSTS
Register Description: Transmit Buffer ‘B’ Status
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Berr
EOF
EOB
Bit 7
Berr – Bus error (set by the CD2231, and cleared by the host)
0 = No bus error
1 = Bus error was detected on the last transfer
Bit 6
EOF – End of frame (set and cleared by the host)
0 = This buffer is not the last in frame/block.
1 = This buffer is the last in frame/block.
Bit 5
EOB – The end of a transmit buffer (set by the CD2231, and cleared by the host).
The end of a host supplied transmit buffer has been reached.
Bits 4:3
Reserved – must be ‘0’.
Bit 2
map32 – Map all transmit characters from 00–1F (set and cleared by the host)
0 = Use the normal TXACCM map.
1 = Map all characters in the range from 00–1F.
Bit 1
INTR – Interrupt
0 = No interrupt required after the buffer is transmitted.
1 = Interrupt required after the buffer is transmitted.
Bit 0
2231own – Ownership of the transmit buffer (set by the host and cleared by the
CD2231)
0 = Buffer is owned by the host, and not ready for use by the CD2231.
1 = Buffer is owned by the CD2231, and is ready for use by the CD2231.
To start transmission of a buffer, the host must set the ATBADR/BTBADR (Transmit Buffer
Address) and ATBCNT/BTBCNT (Transmit Buffer Count) registers, and then set the 2231own bit.
If the CD2231 is to generate and send the CRC for the frame, the CRC bit in COR1 must be set. If
the buffer contains the end of a frame, the EOF bit must also be set. When the buffer has been sent,
the EOB bit is set by the CD2231, and 2231own is reset, allowing a new buffer to be allocated.
8.6.5.8
A Transmit Buffer Status (ATBSTS) — SLIP/MNP 4 Mode
Register Name: ATBSTS
Register Description: Transmit Buffer ‘A’ Status
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Berr
EOF
EOB
148
Bit 4
Bit 3
Bit 2
0
0
map32
Bit 4
Bit 3
Bit 2
0
0
0
Intel Hex Address: x’5D
Motorola Hex Address: x’5E
Bit 1
Bit 0
INTR
2231own
Intel Hex Address: x’5C
Motorola Hex Address: x’5F
Bit 1
Bit 0
INTR
2231own
Datasheet