CD2231

Manufacturer Part NumberCD2231
DescriptionCD2231 Intelligent Two-channel Lan And Wan Communications Controller
ManufacturerIntel Corporation
CD2231 datasheet
 
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Intelligent Two-Channel LAN and WAN Communications Controller — CD2231
8.6.5.13
B Transmit Buffer Status (BTBSTS) — Async Mode
Register Name: BTBSTS
Register Description: Transmit Buffer ‘B’ Status
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Berr
EOF
EOB
This register contains the status of the associated transmit buffer, and it enables successive buffers
to be passed between the host and the CD2231. Status bits within the register are defined as:
Bit 7
Bus error (set by the CD2231 and cleared by the host CPU)
0 = No bus error.
1 = Bus error occurred on the last transfer; the suspect address is available in
TCBADR.
Bit 6
End of frame (set and cleared by host CPU)
0 = This buffer is not the last in frame/block.
1 = This buffer is the last in frame/block.
Bit 5
The end of a transmit buffer has been reached. This bit is used only for DMA sup-
ported transfer. The end of one of the host supplied transmit buffers has been
reached. This bit is set by the CD2231 and cleared by the host CPU.
Bit 4
Reserved – must be ‘0’.
Bit 3
Append (Asynchronous mode only; set and cleared by the host CPU)
0 = No data is appended to the buffer.
1 = Data can be appended to buffer after tx started.
Bit 2
Reserved – must be ‘0’.
Bit 1
Interrupt
0 = No interrupt required after the buffer is sent.
1 = Interrupt required after the buffer is sent.
Bit 0
Ownership of the transfer buffer (set by the host CPU and cleared by the CD2231)
0 = Buffer not ready to be used by CD2231.
1 = Buffer is ready for CD2231 to transmit.
Datasheet
Bit 4
Bit 3
Bit 2
0
Append
0
Intel Hex Address: x’5D
Motorola Hex Address: x’5E
Bit 1
Bit 0
INTR
2231own
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