CD2231 Intel Corporation, CD2231 Datasheet - Page 93

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CD2231

Manufacturer Part Number
CD2231
Description
CD2231 Intelligent Two-channel Lan And Wan Communications Controller
Manufacturer
Intel Corporation
Datasheet
Intelligent Two-Channel LAN and WAN Communications Controller — CD2231
If IXM = 0, transmission is resumed only after the receipt of an XON character or a
transmit enable command by the CCR (Channel Command register).
If IXM = 1, transmission is resumed after the receipt of any character or a transmit
enable command by the CCR.
Bit 6
TxIBE – Transmit in-band flow control enable
If TxIBE is clear, there is no in-band flow control.
If TxIBE is set, transmission is stopped after the receipt of an XOFF character (cntl-
S or hex 13). Immediately after receiving an XOFF, any character in the Transmit
Shift register or Holding register is transmitted, and then character transmission is
halted. Thus, no more than two characters are sent after receiving an XOFF.
Depending on the IXM bit, either the receipt of an XON (cntl-Q or hex 11) character
or any other character (IXM = 1) restarts the transmission. A transmit enable com-
mand by the CCR also restarts the transmission.
Bits 5:4
Reserved – must be ‘0’.
Bit 3
RLM – Remote loop back
RLM = 1, enables Remote Loopback mode
RLM = 0, disables Remote Loopback mode
Bit 2
RtsAO – RTS automatic output enable
If RtsAO = 1, the RTS* output pin remains enabled during DMA or character bursts
from the transmit FIFO. If the CTS* input pin goes high, RTS* goes high and trans-
mission is stopped after the current burst is completed.
Bit 1
CtsAE – CTS automatic enable
When clear, the transmitter output enable is independent of the CTS* input pin.
When set, the CTS* input pin is evaluated prior to the transmission of each character.
If CTS* is asserted low, that character is transmitted completely. If CTS* is high,
that character transmission is held until CTS* goes low.
Bit 0
DsrAE – DSR automatic enable
When clear, the receiver input enable is independent of the DSR* input pin.
When set, the DSR* input pin is evaluated at the end of each received character. If
DSR* is asserted low, the receiver input is enabled for the next character. If DSR*
is high, the receiver is disabled until DSR* goes low.
8.2.3.3
COR2 — MNP4/SLIP Mode
Register Name: COR2
Register Description: Channel Option Register 2
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
0
0
SLIP, MNP4, and Automatic In-Band Flow Control modes are only available on Revision B and
later devices.
Bits 7:6
Reserved – must be ‘0’. No in-band flow control in MNP4 mode.
Bits 5:4
Reserved – must be ‘0’.
Datasheet
Bit 4
Bit 3
0
0
RLM
Intel Hex Address: x’14
Motorola Hex Address: x’17
Bit 2
Bit 1
Bit 0
RtsAO
CtsAE
DsrAE
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